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Electronic design automation
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#	Item
741	Merging Nodes Under Sequential Observability Michael L. Case1,2 1 Victor N. Kravets3 Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-04-02 23:52:50 Electronic design automation Logic in computer science Theoretical computer science Scan chain Logic optimization And-inverter graph Combinational logic Retiming Algorithm Electronic engineering Formal methods Digital electronics
742	The Way Forward for Electronic Design “As founder of an organization that is transforming the economics and technology of an industry so that we can improve opportunity for millions, I am constantly watching what othe Add to Reading List Source URL: www.cadence.com Language: English - Date: 2013-07-08 19:00:35 Electronics Electromagnetism Application-specific integrated circuit Electronic design automation System on a chip Integrated circuit design Three-dimensional integrated circuit S3 Group Mentor Graphics Electronic engineering Integrated circuits Electronic design
743	Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-07-16 02:15:25 Electronics Diagrams Boolean algebra And-inverter graph Circuit Logic synthesis Topology Boolean function Artificial neuron Electronic engineering Electromagnetism Electronic design automation
744	Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Jie-Hong Jiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-05-01 15:17:53 Digital electronics Electronic design And-inverter graph Retiming Logic synthesis Algorithm Field-programmable gate array Logic gate Parallel computing Electronic engineering Electronic design automation Formal methods
745	SEMINAR SEMINAR DISTINGUISHED LECTURE THURSDAY FEBRUARY 8, Add to Reading List Source URL: www.ece.cmu.edu Language: English - Date: 2012-10-03 11:21:29 Electronic design California Institute of Technology Institute of Electrical and Electronics Engineers Engineering Technology Structure Electronic design automation International nongovernmental organizations Digital electronics
746	FRAIGs: A Unifying Representation for Logic Synthesis and Verification Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, Robert Brayton Department of EECS, University of California, Berkeley {alanmi, satrajit, jiejiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-04-01 15:19:32 Boolean algebra Diagrams Digital electronics And-inverter graph Binary decision diagram Logic optimization Model checking Boolean function Logic synthesis Electronic engineering Electronic design automation Formal methods
747	An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS University of California, Berkeley {alanmi, satrajit, brayton}@eecs.berkeley.edu Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-07-16 00:13:15 Integrated circuits Electronic design Placement Logic synthesis Field-programmable gate array Jason Cong Complex programmable logic device Application-specific integrated circuit Electronic engineering Electronics Electronic design automation
748	Microsoft Word - iwls07-final.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-05-01 11:44:52 Boolean algebra Electronic design automation Formal methods Logic in computer science NP-complete problems Boolean satisfiability problem Binary decision diagram Functional dependency Conjunctive normal form Theoretical computer science Mathematics Mathematical logic
749	The Local Lemma is tight for SAT∗ H. Gebauer †, T. Szab´o ‡, G. Tardos § Abstract Add to Reading List Source URL: www.renyi.hu Language: English - Date: 2013-09-26 08:48:45 NP-complete problems Boolean algebra Boolean satisfiability problem Electronic design automation Logic in computer science Hypergraph Unsatisfiable core Exponential time hypothesis MAX-3SAT Theoretical computer science Mathematics Applied mathematics
750	Scalable and Scalably-Verifiable Sequential Synthesis Alan Mishchenko Michael Case Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-07-28 20:26:28 Electronic design automation Electrical circuits And-inverter graph Diagrams Retiming Automatic test pattern generation Scan chain Combinational logic Sequential logic Electronic engineering Formal methods Digital electronics

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